Research and development for a magnetic memory using a magnetic tunnel junction (a MTJ) has been actively performed. The magnetic memory has excellent characteristics such as high-speed writing, the infinite number of times of rewriting, and nonvolatility. Therefore, the magnetic memory is expected to be used not only for a monolithic memory but also for an embedded memory of a microcomputer and so on. As the magnetic memory, a magnetic random access memory (a MRAM) is exemplified.
As a typical memory cell of a MRAM, a magnetic tunnel junction (a MTJ) which can control a magnetic response is disclosed in Japanese patent publication JP-Heisei 10-4227 A (Patent literature 1: corresponding to U.S. Pat. No. 5,650,958). This s magnetic tunnel junction includes a first electrode, a second electrode, and an insulating tunnel layer. The first electrode includes a substrate, a pinning ferromagnetic layer (a magnetization reference layer) and an anti-ferromagnetic layer. The pinning ferromagnetic layer is formed on the substrate and flat. The anti-ferromagnetic layer is adjacently contacted to the pinning ferromagnetic layer, pins a magnetization direction of the pinning ferromagnetic layer in a preferable direction and prevents the magnetization direction from rotating under the existence of an applied magnetic field. The second electrode includes a flat free ferromagnetic layer (a magnetization free layer) whose magnetization direction can rotate freely under the existence of an applied magnetic field. The insulating tunnel layer (a barrier layer) is arranged between the pinning ferromagnetic layer and the free ferromagnetic layer and allows a tunnel current in a direction perpendicular to the pinning ferromagnetic layer and the free ferromagnetic layer. The insulating tunnel layer has a side portion circumference such that the pinning ferromagnetic layer or the free ferromagnetic layer does not extend beyond the side portion circumference. The pinning ferromagnetic layer and the free ferromagnetic layer do not overlap with the insulating tunnel layer and are kept in respective planes which have an interval therebetween.
This memory cell stores one-bit data as a direction of spontaneous magnetization of the magnetization free layer. For example, a state that the direction of the spontaneous magnetization of the magnetization free layer and the direction of the magnetization of the magnetization reference layer are parallel can relate to a “0” state, and a state that they are anti-parallel can relate to a “1” state. The data reading from the memory cell is performed by detecting a variation of resistance of the memory cell based on the magnetoresistive effect. When a current flows in a direction perpendicular to a film surface of the magnetic tunnel junction to detect the resistance, for example, the resistance is low in the “0” state and the resistance is high in the “1” state. Therefore, for example, by providing reference resistance with a value intermediate between the low resistance and the high resistance and comparing it with the resistance of the data, the state of the data can be determined.
The data writing to the memory cell is performed by making a writing current flow through a wiring line arranged in a memory cell array and applying a current induced magnetic field generated by the writing current. For example, the writing current is made to flow in a word line and a bit line which are arranged perpendicularly to each other above and below the MTJ and the magnetization of the magnetization free layer is inverted by using a combination magnetic field generated by the two currents. This method is called the two-axis writing method. In this writing method, only in the memory cell at the place where the selected word line and the selected bit line intersect, the magnetization is inverted.
The data writing to the memory cell can be performed even if there is only one wiring line for writing. For example, a bit line is arranged below the MTJ and the magnetization of the magnetization free layer is inverted by a magnetic field induced by a bit line current. This method is called the one-axis writing method. Here, in this writing method, it is necessary to select the memory cell to be written by a switch in the memory cell. For example, Japanese patent No. JP 3888463 B (Patent literature 2: corresponding to U.S. Pat. No. 7,184,301 B) discloses a memory cell and a magnetic random access memory. This memory cell includes a first transistor and a magnetoresistive element. The first transistor includes a first gate, a first terminal as one terminal other than the first gate and a second terminal as the other terminal. The magnetoresistive element (MTJ) has spontaneous magnetization whose magnetization direction is inverted based on data to be stored and includes a third terminal as one terminal and a fourth terminal as the other terminal. The first terminal is connected to a first bit line. The second terminal is connected to a second bit line. The first gate is connected to a first word line. The third terminal is connected to a second word line. The fourth terminal is connected to the second terminal. Further, the memory cell may include a second transistor provided between the first transistor and the second bit line and including a second gate, a fifth terminal as one terminal other than the second gate and a sixth terminal as the other terminal. Here, the fifth terminal is connected to the second bit line. The sixth terminal is connected to the second terminal. The second gate is connected to the first word line. The third terminal is connected to the earth instead of the second word line. That is, the memory cell with the 2 Tr-1 MTJ type configuration using two transistors and one MTJ is disclosed.
As a method using a principle other than the current induced magnetic field for the data writing to the memory cell, a magnetization inverting method using the spin orbit interaction is proposed. For example, Japanese patent publication No. JP 2009-239135 A (Patent literature 3) discloses a magnetic memory cell, a magnetic memory device using the same and a magnetic memory method. This magnetic memory cell has a first magnetic layer (a magnetization reference layer) whose magnetization state is fixed as a reference layer, a second magnetic layer (a magnetization free layer) whose magnetization state is varied as a data memory layer, and a tunnel barrier layer (a barrier layer) sandwiched the first magnetic layer and the second magnetic layer. In this memory cell, when the magnetization state of the second magnetic layer is changed, the spin orbit interaction of the second magnetic layer is controlled. Spin orbit interaction control electrodes for applying a voltage to control the spin orbit interaction may be provided in the second magnetic layer. That is, the configuration of the memory cell is disclosed in which the electrodes to control the spin orbit interaction is arranged at both ends in a side direction of the magnetization free layer and a domain wall in the magnetic layer is made to move by a low current flowing in an upward/downward direction perpendicular to the side direction based on the spin orbit interaction. An effective magnetic field and a domain wall motion based on the spin orbit interaction are also described in a non-patent literature 1 (Physical Rev. B, vol. 77, 214429 (2008)) and a non-patent literature 2 (Nature Mat., vol. 9, p230 (2010)).
As a related technique, Japanese patent publication No. JP 2008-166689 A (Patent literature 4: corresponding to the U.S. Pat. No. 7,608,901 B) discloses a spin transistor using a leakage magnetic field. This spin transistor using the leakage magnetic field includes a semiconductor substrate portion, a first electrode and a second electrode, a source and drain, and a gate. The semiconductor substrate portion has a channel layer. The first and second electrodes are separately arranged on the substrate portion with a predetermined interval along a longitudinal direction of the channel. The source and drain is composed of ferromagnetic bodies separately arranged with a predetermined interval and magnetized along a longitudinal direction of the channel between the first and second electrodes. The gate is formed on the substrate portion between the source and drain and adjusts spin directions of electrons passing through the channel. The spins of electrons passing through the channel layer are uniformed by the leakage magnetic field of the source at a lower portion of the source and filtered by the leakage magnetic field of the drain at a lower portion of the drain.
Further, Japanese patent publication No. JP 2007-81359 A (Patent literature 5: corresponding to the U.S. Pat. No. 7,307,299 B) discloses a spin transistor using a spin-orbit coupling induced magnetic field. This spin transistor includes a substrate portion, a source and drain, and a gate. A channel is formed in the substrate portion. The source and drain are separately arranged on the substrate portion and are composed of ferromagnetic materials whose magnetization directions are the same. The gate is formed on the substrate portion and adjusts spin directions of electrons passing through the channel. The magnetization directions of the source and drain are perpendicular to a longitudinal direction of the channel.
Furthermore, International publication No. WO 2007/111319 A (Patent literature 6) discloses a MRAM using a spin injection writing method. This MRAM includes a first magnetoresistive element and a reading circuit. The first magnetoresistive element includes a first fixed ferromagnetic layer (a magnetization reference layer), a first non-magnetic layer (a barrier layer) and a first free ferromagnetic layer (a magnetization free layer) laminated in this order. In the first magnetoresistive element, data can be written as a magnetization direction of the first free ferromagnetic layer which is changed by using the spin injection. In the reading operation, the reading circuit reads the data of the first magnetoresistive element based on a resistance value of the first magnetoresistive element. The resistance value can be acquired by making a reading current flow between the first fixed ferromagnetic layer and the first free ferromagnetic layer. By applying the reading current and reading the data a plurality of times, the reading circuit determines one reading data and determines an applying direction of the reading current at the second and subsequent times of the plurality of times based on the previously read data such that the magnetization of the free ferromagnetic layer is not inverted.